This invention relates to microelectronic devices incorporating conductive, connecting straps. More particularly, it is concerned with the method and structure for forming such a device incorporating low-resistivity straps between conductive regions.
The growing use of silicides (e.g. titanium silicide) in microelectronic devices is well known. Silicides, among other uses, are used to diminish contact resistivity for conductor regions such as at moats and gates. Silicides are also used for the formation of local interconnects or straps to reduce sheet resistivity in the interconnect. One method of using silicides simultaneously for these types of applications is to lay down a blanket of titanium (or other silicide-forming metal) followed by a blanket of less conductive material, for example noncrystalline silicon. The noncrystalline silicon and titanium is then patterned so that it remains only where the straps are to be formed. Then the titanium is reacted with the overlying noncrystalline silicon to form titanium silicide. Titanium also reacts with underlying polysilicon and silicon at various sites, not only where local interconnects are formed but at other sites.
To make subsequent contact to other circuit elements (e.g. poly-silicon or poly-Si conductors, poly-Si drain/source regions, poly-Si resistors, metal level conductors), typically the noncrystalline silicon contains dopant which forms an electrical connection from the top surface of the noncrystalline silicon to the underlying titanium silicide. One method of making said subsequent contacts is to deposit doped noncrystalline silicon as the layer reacted with and overlying the titanium silicide.
Another method is to overlay the titanium with an undoped noncrystalline or polycrystalline layer, and selectively dope the areas where a connection is desired.
One problem that has been found with the technique of forming straps and silicided moats and gates simultaneously is that such a method constrains the initial titanium deposition to be a certain minimum thickness in order to achieve acceptable silicide sheet resistivity at moats, gates, and any other site where the silicide is to be formed. Another problem is that since titanium is blanket deposited for simultaneous creation of contacts and straps, one area of the device cannot be silicide-connected to another if an unrelated, exposed conductor is interposed. That is to say, such an interconnect would be shorted to the interposing unrelated conductor. Another problem is that the patterned etch of the overlying noncrystalline silicon must substantially stop on the underlying titanium to maintain a desired titanium thickness over moat and gate regions after etch. However, the selectivity of the silicon etch to underlying titanium is not large such that substantial loss of titanium can result during the silicon etch. Additionally, for thin titanium, the silicon etch might etch through the underlying titanium and even etch into the underlying silicon moat regions. Yet another problem with this technique is that titanium necessarily reacts with underlying materials such as oxide in locations without overlying noncrystalline silicon. This reaction with other materials such as oxygen or nitride could lead to the formation of compounds not as easily removed--for example titanium oxide or titanium oxide nitride (Ti-O-N). Filaments of such undesirable compounds as titanium oxide nitride may not be easily removed and can often lead to undesirable shorting.
Another problem that has been discovered relates to connecting two or more connected conductor regions of semiconductor doped with different impurity type and making a further interlevel connection with subsequently formed circuit elements. One method of connecting the conductor regions while enabling further interlevel connections is to deposit doped noncrystalline silicon. In that instance, during subsequent processing steps, the impurities from the overlying doped deposited noncrystalline silicon can diffuse through the titanium silicide, possibly resulting in counterdoping an adjacent conductor region of opposite doping type. Another method existing in the prior art for making subsequent interlevel connection is to deposit undoped noncrystalline silicon, and subsequently mask and dope to make electrical connection from the underlying silicide to the top surface of the undoped noncrystalline silicon. If it is desired to use arbitrary or only a single-type dopant for the interlevel connections, then such connections cannot be made directly above underlying circuit elements without carrying the aforementioned counterdoping risks. Such a connection scheme requires additional, non-overlying, area be allocated for the interlevel connections. Another problem with this method is that a mask must be used to add dopants to the undoped noncrystalline silicon.
What is needed then is a method which allows for formation of silicided interconnects yet also allows the silicided interconnect to be as thin as necessary. This allows the interconnects to practically overlie unrelated conductors. Also needed is a method wherein titanium will not be reacted in such a manner as to form undesirable compounds which cannot be removed and possibly result in undesired shorting. Also needed is a method whereby the interconnect can be patterned and etched with high selectivity to underlying layers. Furthermore, a method is needed for which a silicided interconnect can be formed independently of gate and moat silicidation.
Additionally, a method is needed which allows for formation of silicided interconnections, yet also allows interlevel connections to be placed above circuit elements, without counterdoping said circuit elements and without requiring additional bar area, regardless of doping process or dopant type. In the preferred embodiment, this process is self-aligning to underlying circuit elements, and does not require any additional masking step for the doping process.